module IF
(
    input clk, input rst,
    input [7:0] PC_in,
    output [7:0] PC_out,
    
    output [15:0] Instr_out,
    input [15:0] Instr_in
);

    assign  PC_out= PC_in;
    assign  Instr_out=Instr_in;
    
endmodule

